1. Field of the Invention
The present invention generally relates to a method of fabricating a semiconductor device, particularly to a method of fabricating a semiconductor device including a pad contact formed by self-alignment.
2. Description of the Background Art
Due to microminiaturization of memory cells in accordance with the larger scale integration of the semiconductor device, it has become difficult to form a contact at the gap between interconnections by means of only a photoresist mask without developing any short-circuiting of the wiring. Self-alignment is known as one technique to form a contact at the gap between interconnections without developing shorting therebetween. A self-aligning contact technique for a semiconductor device employing self-alignment is disclosed in Japanese Patent Laying-Open No. 2001-284452 as conventional art.
FIGS. 47-52 show the steps of the self-aligning contact technique for a semiconductor device disclosed in Japanese Patent Laying-Open No. 2001-284452. FIGS. 47, 48 and 50-52 are sectional views, and FIG. 49 is a plan view thereof.
Referring to FIG. 47, 2001 and 2002 designate a memory cell region and a peripheral circuit region, respectively, of a DRAM (Dynamic Random Access Memory) device. An element isolation film 113 that defines an active region is formed at a predetermined region of a semiconductor substrate 111. On semiconductor substrate 111 where element isolation film 113 is formed, a gate oxide film 115, a word line 117 formed of a conductor, a capping insulation film 119, and a hard mask pattern 121 are sequentially formed. Capping insulating film 119 and hard mask pattern 121 are formed of a silicon nitride film and a silicon oxide film. Accordingly, word line patterns 123a and 123b, each formed of word line 117, capping insulation film 119 and hard mask pattern 121, are configured at the memory cell region and the peripheral circuit region, respectively. Using word line patterns 123a and 123b, and element isolation film 113 as a mask, n type impurities are implanted into the active region to form impurity regions 124a, 124b and 124 of low impurity concentration.
Referring to FIG. 48, a spacer 125 which is a silicon nitride film is formed on the sidewall of word line patterns 123a and 123b. In the peripheral circuit region, using word line pattern 123b, spacer 125 and element isolation film 113 as a mask, n type impurities of high dosage are implanted to form an LDD type source/drain region 126. An etching stop film 127 is formed so as to cover semiconductor substrate 111, spacer 125 and hard mask pattern 121. Etching stop film 127 is formed of a silicon nitride film having an etching selectivity of at least a predetermined level with respect to an interlayer insulation film 129 that will be formed at a subsequent step. Interlayer insulation film 129 formed of, for example, an oxide film of high density, is disposed so as to cover etching stop film 127. Interlayer insulation film 129 having a relatively thin thickness is disposed on the memory cell region of high pattern density.
FIG. 49 is a plan view of the memory cell region of semiconductor substrate 111 at the surface side. The cross section taken along line L—L in FIG. 49 corresponds to the cross section of the memory cell region shown in FIGS. 47, 48, and 50-52. Referring to FIG. 49, a plurality of active regions 101 are formed in semiconductor substrate 111. A plurality of word line patterns 123a are formed so as to transverse active region 101. On interlayer insulation film 129 is provided an etching mask having a mask pattern 105 of a bar shape.
Referring to FIG. 50, interlayer insulation film 129 is subjected to anisotropic etching using the etching mask with mask pattern 105. Then, etching stop film 127 is etched to form self-aligned pad contact holes H1 and H2.
Referring to FIG. 51, a conductor film 131 of polysilicon, for example, is formed so as to fill self-aligned pad contact holes H1 and H2, and cover word line pattern 123a. 
Referring to FIG. 52, the entire surfaces of conductor film 131 and interlayer insulation film 129 are etched by chemical mechanical polishing until the top surface of word line pattern 123a in the memory cell region is exposed. Thus, conductive pads 131a and 131b are formed in the memory cell region. An upper interlayer insulation film 133 is formed on conductive pads 131a and 131b and word line pattern 123a. Upper interlayer insulation film 133 is given a pattern to form a storage node contact 135 reaching conductive pad 131a. 
By such a self-aligning contact technique through self-alignment, word line 117 which is the gate line is prevented from being etched by virtue of etching stop film 127 in the anisotropic etching step of interlayer insulation film 129 since etching stop film 127 has an etching selectivity of at least a predetermined level to interlayer insulation film 129. In the subsequent etching step of etching stop film 127, capping insulation film 119, hard mask pattern 121 and spacer 125 of sufficient thickness remain at the top face and both side faces of word line 117. Therefore, conductive pads 131a and 131b can be formed in self-aligned pad contact holes H1 and H2 avoiding shorting of word line 117.
In the above-described process of self-aligned contact technique, the entire surfaces of conductive film 131 and interlayer insulation film 129 are etched by chemical mechanical polishing until the top surface of word line pattern 123a is exposed. By this step, conductive pads 131a and 131b formed between respective word line patterns 123a are electrically isolated from each other to prevent shorting between the pad contacts.
In the above self-aligned contact technique, conductor film 131 and interlayer insulation film 129 must be polished simultaneously through chemical mechanical polishing in the formation of self-aligned pad contact holes H1 and H2. This polishing must be conducted until the top face of word line pattern 123a in the memory cell region is exposed, taking into consideration variation in the film thickness of interlayer insulation film 129. In the case where the thickness of interlayer insulation film 129 varied so much that polishing down to the predetermined position could not be conducted, conductive film 131 will remain on top of word line pattern 123a. This may cause conductive pads 131a and 131b to develop short-circuiting with each other.
On the other hand, in the case where polishing is conducted deeper than the predetermined position, capping insulation film 119 and hard mask pattern 121 which are the protection film may be completely etched away to result in exposure of word line 117. This exposure of word line 117 will cause shorting to be developed between word line 117 and conductive pads 131a and 131b. 
Reflecting the microminiaturization of memory cells during the past several years, the distance between word line patterns 123a has become smaller. In order to reduce the aspect ratio of self-aligned pad contact holes H1 and H2 in such state of affairs, the height of word line pattern 123a must be designed as low as possible. In many cases, this imposes limitation on the film thickness of capping insulation film 119 and hard mask pattern 121. It is for this reason that the possibility of short-circuiting between word line 117 and conductive pads 131a and 131b becomes higher.